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We proudly announce the launch of newly improved MICROWIND version 3.8 with many new and exciting features.

    New license management system which is more simple to deploy and operate.  
    Supports latest Windows OS (32/64 bit).  
    Introduction of FinFET technology with 14nm design rules.  
    New layout structure, design rules and visualization of FinFET transistors.  
    Improvised compact metal router for Verilog netlist.  
    Routing space saving upto 20% with new compact router.  
    Multiple Verilog file compilation with layout position control.  
    Verilog netlist restructure with options of gate and wire.  
    Improved 3D view with options to hide & view different layers.  
    Convert and visualize MOS layout in schematic (with limited transistors).  
    Convert MOS layout into schematic format for DSCH or SPICE analysis.  
    New DRC lister, now visualize DRC errors and navigate to error location with ease.  
    Add dummy gates for manufacturability for DSM technologies.  
    Now take pictures of simulation results with click of a button.  
    Dump simulation results in CSV format for statistical analysis.  
    Increased simulation run (by 2x) option.  
    Improved help file.  
    Improve drawing speed.  
    Enhanced navigational features.  
    DSCH : Better control on SPICE file generation and executing them.  
    ..many more improvements in software function & operation.  
         
      Lite version evaluation available from April 2017 for test purpose.  
         
         
 

Click here to evaluate the lite version of MICROWIND