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Huge technology support till 22 nanometers. |
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Sub-micron, deep-submicron, ultra
deep-submicron, nanoscale technology support. |
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Design-error-free cell library (Contacts,
vias, MOS devices, etc.). |
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Advanced macro generator (Capacitor, MOS
transistor, matrix, ROM, pads, inductors, path,
etc.) |
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Virtual components library (R,L,C, etc) for
faster simulation response |
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Incredible translator from logic expression
into compact design-error free layout. |
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Powerful automatic compiler from Verilog
structure circuit into layout. |
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Built-in extractor which generates a SPICE
netlist from layout. |
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Extraction of all MOS width and length. |
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Parasitic capacitance, inductance, crosstalk
and resistance extracted for all electrical
nodes.
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Modular design support with insert mask
layout facility. |
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Import/Export CIF layout from 3rd party
layout tools.
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Supports up to 100,000 elementary boxes. |
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Lock & unlock layers to protect some part of
the design from any changes.
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Support upto 8 metal layers for DSM
technologies. |
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Global delay evaluation of circuit with
facility to dump RC values. |
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Global cross talk analyzer. |
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Inversion of diffusions boxes. |
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Easy label listing. |
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Enhanced mathematical signal description for
advance users. |
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Zoom in navigator. |
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Enhanced memory utilization for faster
simulation. |
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Silicon atom viewer with 3D support allows
students to understand Si atom structure. |
