Introduction of FinFET technology with 14nm design rules.
New license management system which is easy to
deploy and operate.
Supports Windows 7/8/10 operating systems with 32/64 bit.
New layout structure, design rules and visualization of
Improvised compact metal router for Verilog netlist.
Routing space saver with new compact router.
Multiple Verilog file compilation with
layout position control.
Verilog netlist restructure with options of gate and wire.
Improved 3D view with options to hide &
view different layers.
Convert and visualize MOS layout in schematic
(with limited transistors).
Convert MOS layout into schematic format for
DSCH or SPICE analysis.
New DRC lister, now visualize DRC errors and
navigate to error location with ease.
Add dummy gates for manufacturability
for DSM technologies.
Take pictures of simulation results with click of a button.
Dump simulation results in CSV
format for statistical analysis.
Increased simulation run (by 2x) option.
Convert MOSFET to FinFET command.
Improvised cell compiler.
Improved and new Help file.
Improve drawing speed.
Enhanced navigational features.
Many improvements in software function & operation.