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Here are some of questions and their respective
answers which are generally put up on our tools. |
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Sr. No. |
Question |
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Answer |
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DSCH |
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Q1 |
Can Wires be connected at user-defined
angles? |
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Yes, to have any angle for the
connection lines, open file menu go to the
properties option, select misc. option in which
select allow any angle of contact.
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Q2 |
How
to count the number of symbols, nodes,
wires used in schematic? |
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To
count the resources used in the schematic, go to
properties option in file menu, in which go to
general properties where you can see the
resources used by schematic.
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Q3 |
Can we generate
SPICE netlist of DSCH schematic? |
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Yes, to generate the
SPICE netlist for the given schematic, go to the
file menu and select the generate SPICE file option.
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Q4 |
Can we see the
Verilog module of the particular symbol? |
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Yes by double
clicking on the symbol you can see its Verilog
module in symbol properties.
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Q5 |
Can we see the
complete netlist of the schematic? |
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Yes, to see the
complete netlist of the schematic go to the view
menu in which select the design hierarchy
option.
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Q6 |
Can we use the
third party simulation tool for the functional
simulation of the schematic? |
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Yes, you can use the
third party simulation tool like modelsim by
converting the schematic into Verilog file
and we can use that Verilog file for the
simulation.
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Q7 |
Can we see the
symbol state at the time of simulation? |
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yes you can see the
state of the individual symbol by selecting
symbol state option in the simulation control
window.
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Q8 |
Can we see timing
simulation of the schematic? |
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Yes, you can see the
functional (timing) simulation of the schematic, by
opening it in the waveform editor provided.
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Q9 |
Can we control the
simulation parameters like wire delay, gate
delay etc?
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For user specified
parameters create your own technology file, save
it and import it when using DSCH.
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Q10 |
Can we change the
value of Vdd (i.e. 1.2 V for 0.12um
technology) while extracting the
spice netlist from schematic?
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Double click on
the VDD symbol,
edit the tech. Vdd which would be inserted in the spice netlist. |
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Q11 |
How to save the
extracted spice netlist? |
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spice file is
saved automatically at the time of extraction
with a ".CIR" extension
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Q12 |
Can we go for higher (level) MOS model spice netlist extraction? |
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Yes, the models can
be updated in<<spice lib>> or user can go for
his/her own library by adding the text <<lib.<lib
name>> as the label in the design.
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Q13 |
Can we import SPICE
netlist? |
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No, DSCH can not import
the SPICE net list as of now.
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Q14 |
Can we import
schematic from another file? |
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Yes, by
insert menu<user symbol> option. |
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Q15 |
How to find
propagation delay? |
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To find out longest
propagation delay between input and output go to
simulate and click
on <find
critical path> option.
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Q16 |
How
to check proper connectivity between symbols? |
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We
can check proper connectivity by the command
:-
Simulate>Check
Floating Lines.
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nanoLamda |
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Q17 |
Can we go for twin
tub fabrication technology? |
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No, there are
certain limitations of the twin tub technology
and
N-well technology is world wide preferred in the
foundries. So we provide N-well technology.
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Q18 |
Can we modify or create our own technology file? |
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Yes you can have your own
technology file or modify the existing technology file by opening it in notepad and
save it as ".rul" file.
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Q19 |
Can we edit to one
particular layer and keep others protected in
nano lambda?
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Yes, by using the
'Protect Layer' option from the 'Edit' menu you
can protect selected layers and edit others. |
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Q20 |
Can we generate bus in
the layout editor (nanolambda) ? |
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Yes, you can
generate bus of the desired parameters by going to the layout generator window from
layout palette, selecting the bus menu giving the
desired bus parameters and pressing the generate bus button.
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Q21 |
Can we import spice
netlist? |
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No, but you can export your layout in spice file format.
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Q22 |
How to import
complete layout from other file? |
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By using
'insert
layout' option from the file menu we can insert complete
layout at the right side of the current layout.
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Q23 |
How to find the
percentage of memory and area used or remaining
while designing? |
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You can find the
percentage of memory and area used or remaining
while designing
from the 'properties' option in the file menu. It gives
the number of devices and nodes.
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Q24
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How
to see critical path of a particular node? |
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By double clicking
on the particular node or from 'view electrical node'
option in the view menu. And to unselect press escape.
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Q25 |
How to remove
lambda grid? |
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By disabling the
lambda grid from the view menu.
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Q26 |
How to get the
number of MOS devices and their sizes? |
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To
view the MOS list, go to the view menu and
select the MOS list option.
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Q27 |
How to move or copy
a particular layer ? |
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Go to
the'copy (move)' from the edit menu , select particular layer and perform
your operation.
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Q28 |
How to generate the
array of identical devices? |
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First go to the
edit menu ,select 'duplicate XY' option ,then select
the portion you want to duplicate ,now give the
multiplication factor for both x and y or you
can also give the data to the array in the
hexadecimal format.
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Q29 |
Why buried
layers are not shown in the technologies beyond the
90nm technology?
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Because buried
layers does not exists with these technologies. |
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Q30 |
How to connect the
two nodes with continuous path? |
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To
generate the continues path go to the 'layout
generator', select the 'path' option' then give
the desire parameters like width, number of
contacts, metal for the path etc.
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Q31 |
How to simulate
design with virtual capacitor? |
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By using the
capacitor symbol present in the palette and assigning value
to it.
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Q32 |
Can we edit the properties of the MOS FETs
used in the design? |
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Yes, from the layout generator you can change the
properties (low leakage high speed, high voltage
) of the MOS FETs used in the design.
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Q33 |
Does it supports
series or parallel combination of identical
devices? |
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Yes, to choose this option we have to mention
number of figures in MOS layout generator.
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 Goto
Top |
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Prothumb |
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Q34 |
Can we give input
in the form of PWL (Piece Wise Linear)? |
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To give input in
the form of PWL select the visible node option
from the
palette, select the PWL option and give
the desired parameters.
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Q35 |
Can user give some
mathematical function to the input wave? |
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Yes, user can give
the mathematical function by selecting visible
node from the palette, in visible node window
select the math option to give the mathematical
function as input.
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Q36 |
How to measure the
amount of the cross talk in the simulation? |
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Goto to analysis menu and click on Cross Talk
Analyzer. |
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Q37 |
Can user set
his/her time scale for the simulation (like
simulate for 11.5ns)? |
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Yes, by the commands:-
simulate<simulation parameter> <models
parameters ><Simulation length>. |
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Q38 |
Why does simulation
runs although there are design rule errors? |
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To give you freedom
to run what you want, and not what the tool
want. |
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Q39 |
Why the color of
background needs to be changed when we give
print command?
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Just to get better layout
visibility. |
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Q40 |
Why does the power dissipation changes every
time we press the 'more' option in the
simulation window? |
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Because it shows
the power dissipation in that particular time
frame only. |
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Goto
Top |
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Protutor |
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Q41 |
Can user set
his/her
own W/L specifications for the MOS
characteristics study in protutor? |
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User can open the .MES
file with notepad and give his specification in
that file.
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Q42 |
How to verify graph
with the standard measures? |
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We can verify graph
with the standard measures by selecting add
measures option in protutor window.
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Q43 |
Can we find crosstalk capacitance and voltage
present in the layout. |
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Yes,
we can
find crosstalk capacitance and Voltage in the
layout by using view>electrical node option.
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Goto
Top |
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VirtualFab |
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Q44 |
Can we see the
cross-sectional view from different horizons? |
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Yes, we can,
wherever we give the cut on the substrate it
gives the cross-sectional view over
there.
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Q45 |
Can we see the 3D
view of layout at different angles? |
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Yes, we can, using
'3D view Open GL' option from the 3D view window
we can observe layout at
different angle. |
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Goto
Top |
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Verilog Compiler |
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Q46 |
How can we control
the padding of I/Os? |
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We can control the
padding by setting pad generation either as free
placement in which by default pad position is
set or by the loading the IBIS file in which pad
assignment is planned before going for the
compilation of the file.
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Q47 |
Q1 How
can we give size parameters in the one line
compiler? |
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You can not directly
give the size parameters in the one line
compiler.For that you have to set the compiler
for the desired size, then go for the one
line compilation.
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Q48 |
How can we get the
inverted output of the layout? |
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The one
line compiler in the compile menu will join an
inverter at the output of the layout and we can have the
inverted output.
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Goto
Top |
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MEMsim |
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Q49 |
How can we see
discharge of the floating gates
of the memories? |
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To discharge the floating gates of the memory,
go to Simulate menu and select 'discharge the
floating gate' option. |
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Q50 |
How can we build
the EEPROM with the help of Microwind? |
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To build the EEPROM
go to the layout generator window, select the MOS
option and go for the double gate devices to
generate the floating gate MOS.
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Goto
Top |
