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Here are some of questions and their respective answers which are generally put up on our tools.

Sr. No.

Question      Answer
  DSCH    
Q1 Can Wires be connected at user-defined angles?   Yes, to have any angle for the connection lines, open file menu go to the properties option, select misc. option in which select allow any angle of contact.
 
Q2 How to count the number of symbols, nodes, wires used in schematic?  

To count the resources used in the schematic, go to properties option in file menu, in which go to general properties where you can see the resources used by schematic.
 

Q3 Can we generate SPICE netlist of DSCH schematic?   Yes, to generate the SPICE netlist for the given schematic, go to the file menu and select the generate SPICE file option.
 
Q4 Can we see the Verilog module of the particular symbol?   Yes by double clicking on the symbol you can see its Verilog module in symbol properties.
 
Q5 Can we see the complete netlist of the schematic?   Yes, to see the complete netlist of the schematic go to the view menu in which select the design hierarchy option.
 
Q6 Can we use the third party simulation tool for the functional simulation of the schematic?   Yes, you can use the third party simulation tool like modelsim by converting the schematic into Verilog file and we can use that Verilog file for the simulation.
 
Q7 Can we see the symbol state at the time of simulation?

  yes you can see the state of the individual symbol by selecting symbol state option in the simulation control window.
 
Q8 Can we see timing simulation of the schematic?   Yes, you can see the functional (timing) simulation of the schematic, by opening it in the waveform editor provided.
 
Q9 Can we control the simulation parameters like wire delay, gate delay etc?
 
  For user specified parameters create your own technology file, save it and import it when using DSCH.
 
Q10 Can we change the value of Vdd (i.e. 1.2 V for 0.12um technology) while extracting the spice netlist from schematic?
 
  Double click on the VDD symbol, edit the tech. Vdd which would be inserted in the spice netlist.
Q11 How to save the extracted spice netlist?   spice file is saved automatically at the time of  extraction with a ".CIR" extension
 
Q12 Can we go for higher (level) MOS model spice netlist extraction?   Yes, the models can be updated in<<spice lib>> or user can go for his/her own library by adding the text <<lib.<lib name>> as the label in the design.
 
Q13 Can we import SPICE netlist?   No, DSCH can not import the SPICE net list as of now.
 
Q14 Can we import schematic from another file?   Yes, by insert menu<user symbol> option.
Q15 How to find propagation delay?  

To find out longest propagation delay between input and output go to simulate and click on <find critical path> option.
 

Q16 How to check proper connectivity between symbols?    We can check proper connectivity by the command :- Simulate>Check Floating Lines.
 
  nanoLamda    
Q17 Can we go for twin tub fabrication technology?   No, there are certain limitations of the twin tub technology and N-well technology is world wide preferred in the foundries. So we provide N-well technology.
 
Q18 Can we modify or create our own technology file?  

Yes you can have your own technology file or modify the existing technology file by opening it in notepad and save it as ".rul" file.
 

Q19 Can we edit to one particular layer and keep others protected in nano lambda?
 
  Yes, by using the 'Protect Layer' option from the 'Edit' menu you can protect selected layers and edit others.
Q20 Can we generate bus in the layout editor (nanolambda) ?   Yes, you can generate bus of the desired parameters by going to the layout generator window from layout palette, selecting the bus menu giving the desired bus parameters and pressing the generate bus button.
 
Q21 Can we import spice netlist?   No, but you can export your layout in spice file format.
 
Q22 How to import complete layout from other file?   By using 'insert layout' option from the file menu we can insert complete layout at the right side of the current layout.
 
Q23 How to find the percentage of memory and area used or remaining while designing?   You can find the percentage of memory and area used or remaining while designing from the 'properties' option in the file menu. It gives the number of devices and nodes.
 
Q24  How to see critical path of a particular node?   By double clicking on the particular node or from 'view electrical node' option in the view menu. And to unselect press escape.
 
Q25 How to remove lambda grid?   By disabling the lambda grid from the view menu.
 
Q26 How to get the number of  MOS devices and their sizes?   To view the MOS list, go to the view menu and select the MOS list option.
 
Q27 How to move or copy a particular layer ?   Go to the'copy (move)' from the edit menu , select particular layer and perform your operation.
 
Q28 How to generate the array of identical devices?   First go to the edit menu ,select 'duplicate XY' option ,then select the portion you want to duplicate ,now give the multiplication factor for both x and y or you can also give the data to the array in the hexadecimal format.
 
Q29 Why buried layers are not shown in the technologies beyond the 90nm technology?
 
  Because buried layers does not exists with these technologies.
Q30 How to connect the two nodes with continuous path?   To generate the continues path go to the 'layout generator', select the 'path' option' then give the desire parameters like width, number of contacts, metal for the path etc.
 
Q31 How to simulate design with virtual capacitor?   By using the capacitor symbol present in the palette and assigning value to it.
 
Q32 Can we edit the properties of the MOS FETs used in the design?   Yes, from the layout generator you can change the properties (low leakage high speed, high voltage ) of the MOS FETs used in the design.
 
Q33 Does it supports series or parallel combination of identical devices?   Yes, to choose this option we have to mention number of figures in MOS layout generator.
 
     

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  Prothumb    
Q34 Can we give input in the form of PWL (Piece Wise Linear)?   To give input in the form of PWL select the visible node option from the palette, select the PWL option and give the desired parameters.
 
Q35 Can user give some mathematical function to the input wave?   Yes, user can give the mathematical function by selecting visible node from the palette, in visible node window select the math option to give the mathematical function as input.
 
Q36 How to measure the amount of the cross talk in the simulation?   Goto to analysis menu and click on Cross Talk Analyzer.
Q37 Can user set his/her time scale for the simulation (like simulate for 11.5ns)?   Yes, by the commands:- simulate<simulation parameter> <models parameters ><Simulation length>.
Q38 Why does simulation runs although there  are design rule errors?   To give you freedom to run what you want, and not what the tool want.
Q39 Why the color of background needs to be changed when we give print command?
 
  Just to get better layout visibility.
Q40 Why does the power dissipation changes every time we press the 'more' option in the simulation window?   Because it shows the power dissipation in that particular time frame only.
     

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  Protutor    
Q41 Can user set his/her own W/L specifications for the MOS characteristics study in protutor?   User can open the .MES file with notepad and give his specification in that file.
 
Q42 How to verify graph with the standard measures?   We can verify graph with the standard measures by selecting add measures option in protutor window.
 
Q43 Can we find crosstalk capacitance and voltage present in the layout.   Yes, we can find crosstalk capacitance and Voltage in the layout by using view>electrical node option.
 
       
     

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  VirtualFab    
Q44 Can we see the cross-sectional view from different horizons?   Yes, we can, wherever we give the cut on the substrate it gives the cross-sectional view over there.
Q45 Can we see the 3D view of layout at different angles?   Yes, we can, using '3D view Open GL' option from the 3D view window we can observe layout at different angle.
     

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  Verilog Compiler    
Q46 How can we control the padding of I/Os?   We can control the padding by setting pad generation either as free placement in which by default pad position is set or by the loading the IBIS file in which pad assignment is planned before going for the compilation of the file.
 
Q47

Q1  How can we give size parameters in the one line compiler?

  You can not directly give the size parameters in the one line compiler.For that you have to set the compiler for the desired size, then go for the one line compilation.
 
Q48 How can we get the inverted output of the layout?   The one line compiler in the compile menu will join an inverter at the output of the layout and we can have the inverted output.
 
     

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  MEMsim    
Q49 How can we see  discharge of the floating gates of the memories?   To discharge the floating gates of the memory, go to Simulate menu and select 'discharge the floating gate' option.
Q50 How can we build the EEPROM with the help of Microwind?   To build the EEPROM go to the layout generator window, select the MOS option and go for the double gate devices to generate the floating gate MOS.
 
       
     

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