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User-friendly environment for rapid design
of logic circuits. |
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Supports hierarchical logic design. |
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Added a tool on fault analysis at the gate
level of digital. Faults: Stuck-1, stuck-at-0.
The technique allows injection of single
stuck-at fault at the nodes of the circuit. |
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Improved interface between DSCH and
Winspice. |
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Handles both conventional pattern-based
logic simulation and intuitive on screen
mouse-driven simulation. |
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Built-in extractor which generates a SPICE
netlist from the schematic diagram (Compatible
with PSPICETM and WinSpiceTM). |
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Generates a VERILOG description of the
schematic for layout conversion. |
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Immediate access to symbol properties
(Delay, fanout). |
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Model and assembly support for 8051 and PIC
16F84 microcontrollers. |
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Sub-micron, deep-submicron, nanoscale
technology support. |
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Supported by huge symbol library |
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